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12/02/07 Yield myths at 65nm! - FabTech
"Although Intel Corp. plans to start volume production at the 45nm node later this year, the leading-edge node for the rest of the CMOS logic community will be 65nm. This simple statement lays the foundation for a host of misconceptions about the 65nm node having been ‘cracked,' and that volume production at high yields is a given."

AMD 65 nanometre chips available - the inquirer
"The CPUs are marked Revision F2, and the maximum TDP varies between 65W and 89W - in the real world, 55-62W and 72-81W is expected - depending on the number of cores, of course. The advertised features are
Cool'n'Quiet, NX-Flag, SSE3 and Pacifica"

AMD validates 65nm CPU production at Chartered - DigiTimes
"Although AMD appears to be lagging behind its rival on 65nm deployment, the company is fully gearing up for 65nm production and
Chartered should play a critical role in supporting AMD's goal to have 90% of its CPU lineup advance to 65nm production in 2007."

AMD modifies 65nm Athlon 64 X2 roadmap - Digitimes
"The adjusted clock speeds will be for parts including the
Athlon 64 X2 4000+ (2.1GHz), Athlon 64 X2 4400+ (2.3GHz) and Athlon 64 X2 4800+ (2.5GHz), respectively, with the clock speeds splitting the difference between the 90nm existing models - Athlon 64 X2 3800+ and 4000+ (2.0GHz), Athlon 64 X2 4200+ and 4400+ (2.2GHz) and Athlon 64 X2 4600+ and 4800+ (2.4GHz)."

AMD says 65 nm chips due next month - the inquirer
"Another good reason for increased yields is its adoption of Front Opening Shipping Boxes (FOSBs). These keep the wafers almost hermetically sealed for the vast majority of the production process – only exposing them to its cleanroom standard of 100 particles per cubic metre of air on very rare occasions."

AMD to rush to 65-nm technology - EETimes
"Microprocessor vendor AMDs decision to install the new fab 38 in Dresden makes the region around the Saxonian capital a major semiconductor industry center worldwide. EE Times asked
fab 36 manager Udo Nothelfer about the company's road map and potential technological hurdles on the way. "

AMD And IBM Unveil New, Higher Performance, More Power Efficient 65nm Process
"The companies announced that they have successfully combined embedded Silicon Germanium (e-SiGe) with Dual Stress Liner (DSL) and Stress Memorization technology (SMT) on Silicon-On-Insulator (SOI) wafers, resulting in a 40 percent increase in transistor performance compared to similar chips produced without stress technology, while controlling power consumption and heat dissipation."

Chartered Semi to introduce 65 nano chip soon - the inquirer
Chartered has an alliance with Samsung, Infineon and IBM because they all bring different elements to the party. Chartered is jointly developing at East Fishkill for 90, at 65 and at 45 nanometres. And Sony and AMD are in a joint deal at East Fishkill over silicon on insulator."

AMD's 65 nano question solved: it's a second half thing - CNET
"Advanced Micro Devices has been cagey about when it will start to manufacture chips on the 65-nanometer process. Chips cranked out on this process will be faster than current
90-nanometer chips, and likely be smaller too, which will reduce AMD's costs. "

Intel moves into volume with new chips - CNET
"Yonah, a 65-nanometer
dual-core notebook chip, will go into volume production by the end of the year, he added. By the third quarter of 2006, more chips will be produced on the 65-nanometer process than on the 90-nanometer process, the so-called crossover point. "

Spansion to bring forward 65-nm manufacturing - EETimes
"During a presentation on the company’s 1-Gbit NOR flash memory, introduced on a
90-nm process, John Nation, technical marketing manager, said the company would introduce flash memory products on 65-nm process in 2006. This was at odds to the presentation which indicated the end of the first quarter of 2007 as the introduction date for 65-nm manufacturing. "

Intel's Shifting Silicon - Internet News
"With four
90nm fabs in production and two 65nm fabs ramping toward the end of 2005, McGregor said Intel also has more capacity than it can use for just IA-32 and IA-64 processors. As a result, Intel said it will begin shifting other products, such as chipsets, to the 90nm process"

AMD runs silicon in 300-mm wafer fab, preps 65-nm process - EE Times
"Processor vendor Advanced Micro Devices Inc. has started running wafers through Fab36, the company's
300-mm wafer fab located in Dresden, Germany and is on course to have commercial production in 2006, according to Tom Sonderman, the company's director of APM technologies."

AMD claims to close CPU process gap - the inquirer
"With Intel thumping its chest in full force about 65 nano technology, AMD shot back with a pithy press release about how it is going to close the process gap this time. Fine, good, no, great, competition is what makes Applied Materials stock go up, and we all win that one, or at least Applied Materials stock holders win"

Intel’s 65-nm Cedar Mill CPU to have power consumption of 65W - DigiTimes
"The power consumption of Intel’s 65-nm single-core Cedar Mill processors is likely to be around 65W, down from the around 115W of the current Prescott CPUs, according to sources at Taiwan motherboard makers who have seen Intel’s CPU roadmap. The Cedar Mill is scheduled to be launched in early next year."

AMD claims it's catching Intel on 65 nano tech - the inquirer
"AMD is on track to produce 65 nanometre processors, he said. While he said that Intel is clearly behind AMD on 64-bit technology, AMD won't be that far behind the firm on the move to 65 nanometre.  Reliable sources inside Intel claim Intel has already got 65 nanometre versions of its chips taped up and running at its development fabs."

Intel 65nm desktop, server CPUs 'up and running' - The Register
"Intel has already said, of course, that it has working 65nm silicon and late last year demonstrated its 'Yonah' dual-core mobile processor, the successor to today's single-core Pentium M 7xx series. Intel has said it will ship Yonah in limited numbers late this year, with volume production taking place in 2006."

STMicroelectronics Wins the Race to Deliver First 65-nm CMOS Design Platform
STMicroelectronics today announced the important milestone of delivering a 65-nm (0.065-micron) CMOS design platform, which allows its designers and customers to start developing next-generation System-on-Chip (SoC) products for low-power, wireless, networking, consumer, and high-speed applications. In addition, ST announced the completion of a design, or tape-out, of a 65-nm complex system- on-chip to fully demonstrate its advanced technology.

Completing the development of the basic production process at Selete - PC Web

AMD flashes open dual core 65 nano kimono - the inquirer
"We said that presumably when AMD moved to 65 nanometre technology, which it has said it will be able to do next year, it would be able to get four cores on the same wafer rather than just two."

Intel 65nm and Beyond (or Below) - AnandTech
"Moving to a 65nm transistor requires a 65nm lithography process. We are already seeing devices being built into silicon with features smaller than the wavelength of the light used in the lithography process. As it will be somewhere near 2009 before Intel has their EUV (13nm light wavelength) technology up and running, working with such small features requires some special masking tricks"

65-nm Intel CPUs due in late '05 - EE Times
Moore's Law is alive and kicking at Intel Corp., which on Monday (Aug. 30) announced plans for volume production of its 65-nanometer processors. Now that Intel has successfully crossed over to 90-nm manufacturing, it expects to begin volume manufacturing of 65-nm processors in late 2005, with transistors that provide a 1.4x increase in raw frequency compared with the 90-nm technology. "

Intel: First 65nm Chips. Problems and Prospects -Digit-Life
"Meanwhile, Intel had to resort to multiple engineering tricks to get new chips on the P1264 process, 65nm, where the transistor gate is not wiser than 35 nm (compare to those in the Intel Pentium 4 where they are 50nm wide). It's not only because the company applied the second generation of the strained silicon technology, copper connections and new low-k dielectrics. For the new chips the company had to use the old tools together with the photomask phase shift technology. "
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Intel 65-nm process, including the eight-layer, dual-damascene copper interconnect with a 2.9-k inter-layer dielectric