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AMD & 65nm Technology - 12/16/04
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STMicroelectronics Wins the Race to Deliver First 65-nm CMOS Design Platform

ST completes design of full-complexity 65-nm System-on-Chip technology demonstrator

GENEVA, December  16, 2004 - STMicroelectronics today announced the important milestone of delivering a
65-nm (0.065-micron) CMOS design platform, which allows its designers and customers to start developing next-generation System-on-Chip (SoC) products for low-power, wireless, networking, consumer, and high-speed applications. In addition, ST announced the completion of a design, or tape-out, of a 65-nm complex system- on-chip to fully demonstrate its advanced technology.

ST's full 65-nm library platform includes multiple process options that allow individual cells to be optimized for high performance, low power, or general purpose use. Each option shrinks 90-nm products by half while improving speed up to 30% or reducing leakage by half in operation, thereby reducing power consumption. The platform offers two standard cell libraries, optimized for performance and density, which provide a rich portfolio of more than 1,500 cells; multiple voltage I/O cells; multiple memories; and analog IP (Intellectual Property). The cells support densities of more than 800,000 gates per square millimeter and a core supply of 1.0V or 1.2V, with metal pitches of 0.20-micron and from six to ten metal routing layers.

"Being the first to deliver a 65-nm design platform validates our alliance strategy, in general, and the efforts of the Crolles2 Alliance, in particular," said Didier Chapuis, Group Vice President, Platform Development at STMicroelectronics. "Our customers' applications will exhibit spectacular performance at affordable costs because we've overcome the challenges to delivering the 65-nm design platform."

Further extensions to the initial platform offering, including
SOI (Silicon-on-Insulator) versions and high-performance integrated passive devices, are at an advanced stage of development and will be available soon.

The new
65-nm CMOS design platform takes full advantage of the multiple features and modularity of the 65-nm process technology developed by the Crolles2 Alliance of STMicroelectronics, Freescale Semiconductor, and Philips Semiconductors. Additionally, several services, developed by the Crolles2 Alliance, are available to ease access to the technology, including: fast prototype cycle time, which is down to less than one week and has been proven for 130-nm ICs; cost reduction in mask sets; and use of e-beam technology, which allows customization without the need for masks. Also, a shuttle multi-project reticle service has started for 65-nm designs.

The
65-nm design platform is fully supported by the industry's leading CAD tools from Cadence, Mentor Graphics, and Synopsys. These tools have all been developed in close cooperation with the R&D teams of the EDA partners.

Further technical information
Features of the library include:

      * A full range of 1.2V, 1.8V, 2.5V I/O cells;

      * Extremely dense embedded memories, including single-port memories
        using 6T-SRAM of 0.5-square-micron area, dual-port memories, and Read-
        Only-Memories;

      * A fully compatible, low-cost process variant, allowing up to 64-Mbit
        of embedded DRAM with a memory cell area of 0.12-square-micron;

      * Power reduction techniques such as adaptive and low Vdd operation,
        power shutdown, and low standby current in standby mode;

      * A broad portfolio of analog and RF IP is under development to cover
        the need for single system super-integration;

      * A variety of complex IP modules such as microcontrollers and digital
        signal processors.

About STMicroelectronics

STMicroelectronics is a global leader in developing and delivering semiconductor solutions across the spectrum of microelectronics applications. An unrivalled combination of silicon and system expertise, manufacturing strength, Intellectual Property (IP) portfolio and strategic partners positions the Company at the forefront of System-on-Chip (SoC) technology and its products play a key role in enabling today's convergence markets. The Company's shares are traded on the New York Stock Exchange, on Euronext Paris and on the Milan Stock Exchange. In 2003, the Company's net revenues were $7.24 billion and net earnings were $253 million.
Intel 65-nm process, including the eight-layer, dual-damascene copper interconnect with a 2.9-k inter-layer dielectric
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