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AMD Athlon 64 FX-60 Review - 04/19/06
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Athlon FX-60 Review - 1

Summary
What happens if the fastest core speed is combined with the most advanced technology - in this case featuring dual cores? For single threaded applications, the obvious answer is nothing much but fortunately, it appears that we are finally getting away from DOS and migrating towards a world dominated by massive multitasking. Dual cores, even more than single cores, have a sheer insatiable hunger for data which increases with any additional speedstep. Using the HyperTransport interface grants the AMD design a substantial advantage over Intel's front side bus with its bidirectional data bus. All of this combined with refined silicon mixtures to further lower the power consumption of the CPU promise the makings of another champion: Enter the FX60.

Does it live up to the expectations? We are about to answer exactly that question!
Just as genius is usually attributed to 5% inspiration and 95% hard work, success does not grow on trees, rather it is the fruit of continuous commitment of resources, capable management and that piece of luck generally described as being in the right place at the right time.

Along these lines, hardly any analyst would have predicted only six years ago that AMD, then on the verge of bankruptcy, could pull of what they did accomplish in the last half dozen years, namely to steal copious market share from Intel to the point where AMD is becoming a serious challenge in the CPU market. Needless to say that it all started with the launch of the Athlon but a one hit wonder does not carry enough clout to usurp the marketplace for more than a very brief period of time.























Whichever way one may look at things, whether it was the somewhat misguided Netburst architecture that undermined Intel's leading position, or whether it was purely and simply the engineering prowess leading to the Athlon64 design with its scalable HyperTransport interface and, more importantly, the integration of the memory controller on the CPU die, none of this matters anymore. What matters is that there is a superior concept that took the enthusiast and gamer communities by storm and caused a domino effect in the white box and finally the large OEM community. With the last Intel-exclusive bastion in the form of Dell finally succumbing to market demands, every single OEM of name and rank finally offers AMD-powered platforms.

It is not without importance that another major movement in the PC industry has been the migration to massive parallel processing. With all due respect to AMD, Intel were the ones to spearhead the subdivision of a single physical core into two logical cores by introducing the concept of HyperThreading. While awkward at first glance, HT does make a difference, especially in the case of the Netburst architecture in that several parallel threads can be scheduled and fed to the execution units like the two strands of a zipper for optimal utilization of the resources available. The primary importance for AMD in this case lies in the weight thrown by Intel onto the software world, forcing the porting of, at least some of the better programs, towards multithreading. It does not require much intuition to make the connection to multicore processors as the next step.

HyperThreading to MultiCores
To spin this a bit further, the situation does not lack a certain amount of irony since the very optimizations that enabled HyperThreading are now what makes AMD's line of dual core processor so successful. At least compared to Intel's current lineup that still relies on the 8086-derived host bus to interface with the core system logic and specifically with the memory controller. Not only is this host bus bi-directional, meaning it can only read OR write at any given point, but also, it is shared between all logical processors. Given the fact that also every single busmaster First Party DMA access needs to utilize the very same bus for ensuring that the data in the main memory space are valid and not resident and modified in the cache (by virtue of a process called snooping), it is almost inconceivable how the architecture with its inherent latencies can even support the current processing power of high-end CPUs. The actual pipeline length of the Prescott / Cedar Mill becomes almost secondary in view of the just mentioned system interface limitations.

This is where AMD's full duplex HyperTransport or LightningDataTransport makes a difference not only for the current generation of CPU but also for future revisions that will push the sheer insatiable hunger for data another notch up. Reads can be executed in parallel with writes, a simple FP-DMA request will be snooped at CPU speed instead of chipset clock rate and even the arbitration of data is executed in the system request interface at CPU speed.

Fast execution on the front end requires, however, a fast backend, and this is where the battle in memory land will become quite interesting. Before long, we will see the transition of AMD, too, towards the DDR2 architecture, driven primarily by cost considerations since DDR and DDR2 pricing has reached parity and, in the near future, will see DDR2 undercut the first generation DDR pricing. Arguably, DDR2 is slower on the level of latencies, on the other hand, the higher densities of memory discreets allow for higher system memory configurations. Another side effect of the higher discreet density embarks on the fact that 1Gbit and higher memory chips use eight internal banks as opposed to the four banks used on DDR and lower density DDR2 chips.

































The importance of the increased number of internal banks is the concurrent increase in open pages that can be maintained, meaning that starting with the
AM2 interface, we will see a doubling of supported open pages per memory slot from currently 8 (dual rank modules) to 16 (if supported by the memory components). Whether this will really make a performance difference remains to be seen, predictably, however, it will have quite an impact on memory power consumption, especially in interleaved accesses.

There is no action without reaction, though, and exactly the just mentioned increase in power consumption has been the reason for the introduction of yet another memory latency dubbed tFAW (four way access window) that will disallow back to back transactions for the simple reason of preventing thermal runaway within the memory chips.

At this point, all we can say is that another turning point is coming up with new technologies and new rules for new possible configurations. With all due respect for academic considerations of the performance swings in the one or the other direction, there is currently no telling how it will all pan out in the end - not even for us here.

Things to come are interesting enough to get carried away with speculations, right now, however, we are still stuck with legacy hardware, meaning DDR1 for the dual core Athlon64 in its latest revision, introducing the FX moniker to the dual core series.
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