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08/25/09 AMD’s Bulldozer Processors to Feature Simultaneous Multi-Threading Technology - Xbilabs
"AMD did not reveal many details about its SMT capability and only said that its Bulldozer processors would support it in 2011. Still, it is rather likely that AMD’s approach may be somewhat different compared to Intel’s HT and may even be of the same kind like Sun Microsystems’ simultaneous multi-threading feature than supports execution of four threads on one physical core."

03/05/09 AMD Re-Schedules Bulldozer Processors to 2011 - Xbitlabs
"The first processor in the Bulldozer family is code-named Orochi and it has more than four cores, more than 8MB of cache and supports DDR3 memory. The Orochi chip will be made using 32nm process technology and is currently due in 2011. Another interesting chip due in 2011 is code-named Ontario, which has two general-purpose x86 cores, built-in graphics processing engine, 1MB of cache and DDR3 memory support. The chip will be based on the code-named Bobcat micro-architecture, which is projected to be very power efficient, and will also be among the first "Fusion" processors that combine x86 and graphics processing on the same chip."

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Bulldozer is the codename AMD has given to one of the next-generation CPU cores after the K10 microarchitecture for the company's M-SPACE design methodology, with the core specifically aimed at 10 watt to 100 watt TDP computing products. Bulldozer is a completely new design developed from the ground up. AMD claims dramatic performance-per-watt improvements in HPC applications with Bulldozer cores. Products implementing the Bulldozer core are planned for release in 2011.

The Bulldozer core, under the M-SPACE design method, can also to be paired with at least one full DirectX compatible GPU core (though AMD did not specify the compatible GPUs, it was presumed to be based on Radeon GPUs), to become part of the Falcon family, a product under the codename "Fusion" label. A new architecture, codenamed Sandtiger, with 8 to 16 Bulldozer cores was also in the works, optimized for servers and HPC applications.

The Bulldozer cores will support most of the instruction sets currently implemented in Intel processors (including SSE4.1, SSE4.2) future Instruction sets announced by Intel (AES, PCLMULQDQ and AVX), as well as future instruction sets proposed by AMD (XOP, FMA4 and perhaps CVT16).

According to the current roadmap, Bulldozer-based implementations built on 32 nm are scheduled to arrive in 2011 for both servers and desktops, as the 16-core Opteron processor codenamed Interlagos and as the quad-core desktop processor codenamed Orochi.
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