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HyperTransport Consortium Announces Suite of HyperTransport 2.0 Devices from AMD, Agilent, Dolphin, FuturePlus, GDA, SiS, ULi, and VIA

SUNNYVALE, Calif. - October. 18 2004 - HyperTransport Technology Consortium, the nonprofit industry organization that manages and promotes low-latency HyperTransport technology, announced today that the first wave of HyperTransport Specification 2.0 compliant devices are now available from a number of member companies. HyperTransport Specification 2.0 defines performance levels of up to 2.8 Gigatransfers/second and mapping to PCI Express. The new products include HyperTransport-enabled 64-bit processors, I/O chipsets, silicon IP, and development tools. The arrival of products conforming to HyperTransport Specification 2.0, which supports up to 22.4 Gigabytes/second aggregate bandwidth, is an important milestone, marking the fastest industry adoption of a new HyperTransport technology specification.

"The industry's rapid adoption of our latest specification is a strong endorsement of the technical advancements embodied in
HyperTransport technology. It also greatly adds to the comprehensive set of HyperTransport-based building blocks that the industry is leveraging in high performance designs," said Mario Cavalli, General Manager of the HyperTransport Technology Consortium. "HyperTransport technology delivers competitive advantage to industry leaders by providing the lowest possible latency, the highest bandwidth and the lowest implementation costs. This is why HyperTransport can be found in applications ranging from high-performance multimedia appliances to supercomputing platforms."

"
HyperTransport technology is the backbone of AMD64 technology with Direct Connect Architecture," said Ben Williams, vice president for enterprise and server/workstation business for AMD's Computation Products Group. "It enables system designers to directly connect AMD64 processors with each other and to high-bandwidth I/O peripherals. The result is an efficient, extremely low latency, and balanced single platform architecture for high-performance systems. We will be implementing HyperTransport 2.0 technology in a range of AMD Opteron and AMD Athlon 64 processors, starting with the AMD Athlon 64 processors 3000+ and 3200+, which are available today."

HyperTransport 2.0 Technology Compatible Products Include:

1)
AMD Athlon 64 processors 3000+ and 3200+ - high-performance processors featuring AMD64 technology with Direct Connect Architecture, integrated DDR memory controller, high-performance on-chip cache, advanced power management and both 32- and 64-bit x86 instruction set support

2) SiS 756/965 Chipset -
HyperTransport-based AMD Althlon64FX/64 microprocessors base chipset supporting HyperTransport interface with 8 and 16-bit wide HyperTransport links with bridge to PCI and PCI Expressx16 and x1, 8-port USB 2.0/1.1 controller, 4-port SATA controller, Gigabit Ethernet/HomePNA interface, AC'97 compliant audio/modem controller, power management functions, dual IDE channels with parallel ATA 133/100 interface and integrated LPC 1.1 interface/RTC/keyboard/mouse controller. Other devices include the SiS755, SiS755FX, SiS760, SiS760GX, SiSM760, SiSM760GX graphics and core logic chipsets.

3) ULi M1689 Single-chip Core Logic Chipset/M1695
HyperTransport 2.0 Tunnel Bridge - The M1689 is a single-chip core logic chipset for Athlon64 and Opteron processors that offers exceptional performance per watt. It includes 8/16 bit HyperTransport 2.0 links, 8X AGP controller, 2-channel Ultra-66/100/133 IDE master controller, 8-port USB 2.0/1.1 controller, I/O APIC controller, Fast Ethernet/HomePNA MAC interface, SATA interface, software modem, 6-channel audio controller and PCI interface. The M1695 is a HyperTransport 2.0 Tunnel Bridge that provides exceptional bandwidth through its various embedded HyperTransport-to-PCI-Express links.

4) VIA K8T890 Northbridge - Integrated support for
HyperTransport 2.0 in the most recent models of the VIA K8 Series core logic chipsets for the AMD Athlon 64 and AMD Opteron 64-bit processors.

5) Dolphin Technology
HyperTransport PHY IP - provides a high-speed HyperTransport physical interface circuit for implementation into custom ASIC or ASSP devices. Dolphin's HyperTransport Rx/Tx I/O macros support up to 1.2 GigaHertz clock rates that provide up to 2.4 Gigabits/second bandwidth. A 1.4 GHz (2.8 Gbs) version is under development.

6) GDA Technologies, Inc. HyperTransport IP Cores - provide enhanced, silicon validated HyperTransport IP cores to support the latest HyperTransport I/O Link Specification, version 2.0. The enhanced IP cores are the industry's highest performance, lowest latency solutions and are designed for reuse and easy integration into a wide range of applications. Key features include HyperTransport cave, host, tunnel and switch/bridge topologies, optimized for standard cell, FPGA and Structured ASIC implementations, supports up to 2.8 Gbits/s line rate, supports Retry protocol for robust transport at high speeds, configurable 16- or 8-bit link interface, software programmable to 2, 4, 8 or 16 bits with a wide range of bandwidth, from 1.6 to 89.6 Gbits/s aggregate bandwidth.

7) Agilent 93000 SOC Series Device Tester - Flexible ATE solution for
HyperTransport device testing in a single scalable platform architecture with software upgradeable speed support with true low-voltage differential and single-ended operation with ultra-fast jitter measurement capability. The Agilent 93000 SOC Series addresses the needs of both thorough device characterization and economic high volume manufacturing testing.

8) FuturePlus Systems
HyperTransport Link Analysis Debug Probe - Enables designers to debug, test and verify compliance of 8 and 16-bit HyperTransport links using Agilent Technologies 16700 and 16900 logic analysis systems. The FS2240 and FS2243 support up to 2.4 Gigatransfers/second as defined by the HyperTransport 2.0 specification.

About HyperTransport Technology

HyperTransport chip-to-chip interconnect technology is a highly optimized, high performance and low latency board-level architecture for embedded and open-architecture systems. It provides up to 22.4 Gigabyte/second aggregate CPU to I/O or CPU to CPU bandwidth in a highly efficient chip-to-chip technology that replaces existing complex multi-level buses. In addition to delivering the industry's highest bandwidth, frequency scalability, and lowest implementation cost, the technology is software compatible with legacy Peripheral Component Interconnect (PCI), PCI-X and PCI Express technologies. HyperTransport technology delivers state-of the-art bandwidth by means of easy-to-implement Low Voltage Differential Signaling (LVDS) point-to-point links, delivering increased data throughput while minimizing signal crosstalk and EMI. It employs a packet-based data protocol to eliminate many sideband (control and command) signals and supports asymmetric, variable width data paths.

About the HyperTransport(TM) Technology Consortium


The HyperTransport Technology Consortium is a membership-based, non-profit organization in charge of managing and promoting HyperTransport Technology. It consists of over 40 member companies, including founding members Advanced Micro Devices, Alliance Semiconductor, Apple Computer, Broadcom Corporation, Cisco Systems, NVIDIA, PMC-Sierra, Sun Microsystems, and Transmeta. Membership is open to any company interested in licensing the HyperTransport technology. It is based on a minimal yearly fee and includes the right to royalty-free use of HyperTransport technology and Intellectual Property.

HyperTransport is a licensed trademark of the HyperTransport Technology Consortium. All other trademarks belong to their respective owners.
HTC Members
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