| AMDboard.com | home | best sellers | glossary | hardware | hot NEWS | links | OC | |
| Your best source for AMD Athlon 64, DDR, Duron, nForce2, nForce3 & Opteron information |
| MPF 2002 Special |
| San Jose CA Articles |
 |
10/28/02 CPU Power Push - eWeek "It's not that Pentium 4 is the wrong processor, it's just that its volume is inherently limited. Intel's parts don't enable new applications." 10/25/02 The INQ's Microprocessor Forum Report - Part 1 - the inquirer "This little thing could make a 64-bit PowerBook - imagine the tomorrow's 64-bit mobile battle: ClawHammer by AMD vs PPC970 by IBM: where's Intel there?" 10/17/02 MemoryLogix claims x86 clone may power portable XBoxes - the inquirer "MemoryLogix is planning to produce an 8086-compatible embedded core aimed at the ARM/XScale market. The processor will run at over 400MHz, and take 6 sq mm in a .13 micron process" 10/17/02 Microprocessor Forum 2002 report - PC Watch 10/16/02 Hammer momentum leaving Itanic stranded - The Register "AMD and Intel packed the floor with their staff at yesterday's server Q&A. Questions from employees, inevitably to the opposition, dominated the session. AMD fielded VP and chip CTO Fred Webber, and Intel put Robert Yung, enterprise platforms CTO into the firing line" 10/16/02 AMD releases Opteron benchmarks - CNET "By contrast, Intel has separate chip families for the 32-bit world and the 64-bit world, a situation AMD's Weber called "a house of cards" during a panel speech. Intel declined to respond to the comment, but stated that it is committed to its chip families." 10/16/02 MPF Day One: Incremental Advances - ExtremeTech "John also showed a popular quote from Gordon Moore—"If the automobile industry advanced as rapidly as the semiconductor industry, a Rolls Royce would get a million miles per gallon, and it would be cheaper to throw it away than to park it". And he mentioned it probably could be the size of a mosquito" 10/16/02 AMD Touts Opteron Performance - eWeek "But rather than compete against other 64-bit products, AMD is positioning Opteron to go head-to-head with Xeon, which sells strongly in workstations and low-end multiprocessor servers. In addition, Opteron is designed to run both 32-bit and 64-bit applications, making it suitable for use with Microsoft Corp.'s Windows operating systems and compatible applications, which is Xeon's target market." 10/16/02 AMD Tips Opteron Benchmarks - ExtremeTech "Weber's disclosure is of "a non-existent product six months out", the Intel spokesman said. "We'll have hyperthreading, (and) a 533-MHz bus…by the time they even think of getting to market. Any prediction they make should be taken with a grain of salt." 10/16/02 Intel describes billion-transistor four-core Itanium processor - EETimes "Crawford went on to describe a hypothetical processor that would contain four Itanium 2 cores and 12 to 16 megabytes of shared cache memory, all connected through a leaf interconnect scheme. Each Itanium 2 processor would contain about 120 million transistors while the cache would carry 700 million to 950 million transistors, bringing the total transistor budget to well over 1 billion, he said" 10/16/02 Four-core Itanium 2 mooted at Microprocessor Forum - the inquirer "INTEL HAS USED the Microprocessor Forum to hype up the Intelgraph Itanic 2 processor, demonstrating how the processor core could be deployed in a foursome, using a shared cache, to effectively create, it says, one processor made up of over one thousand million processors" 10/16/02 Highlights and insights from the Microprocessor Forum - the inquirer "The new PowerPC triples the pipeline length to achieve higher frequencies of 1.4 to 1.8 GHz in the 2nd half of 2003. We'll see at what frequencies Intel and AMD are running by then" 10/15/02 Via to disclose 'Nehemiah' MPU at Microprocessor Forum - EETimes "Based on a 0.13µ process, Nehemiah is a 1- to 1.5-GHz processor, built around copper-interconnect technology. It also includes 64KB of cache and MMX+SSE multimedia instructions" 10/15/02 Processors begin 64-bit push - EETimes "AMD uses a 64-bit prefix in front of X86 instructions to tag a 64-bit operation. The technique requires referring to separate 64-bit registers and extended memory addresses. That method is "very elegant in terms of not disrupting the X86 architecture but may not be able to support mixed 32- and 64-bit operations as well as IBM's approach," said McCarron of Mercury Research" 10/10/02 Microprocessor Forum 2002 Preview - ExtremeTech "Historically, many of the technical sessions can get pretty detailed, going far down into the superscalar out-of-order pipeline depths, and we love it! " |
| Red date for newly added article |
|
 |
| Links |
 |
 |
|
 |
|
|
|
|
|
|
|
|
|
|
|
 |
|
|
|
 |