| Series |
100 Series |
200 Series |
800 Series |
| Scalability |
1-way |
Up to 2-way |
Up to 8-way |
| Performance |
AMD Opteron processor benchmarks |
| Dual-Core Options |
|
| Frequency |
Model Numbers |
| 1.8GHz |
Model 165* |
Model 265* |
Model 865 |
| 2.0GHz |
Model 170* |
Model 270* |
Model 870 |
| 2.2GHz |
Model 175* |
Model 275* |
Model 875 |
| Single-Core Options |
|
| Frequency |
Model Numbers |
| 1.4GHz |
Model 140 |
Model 240 |
Model 840 |
| 1.6GHz |
Model 142 |
Model 242 |
Model 842 |
| 1.8GHz |
Model 144 |
Model 244 |
Model 844 |
| 2.0GHz |
Model 146 |
Model 246 |
Model 846 |
| 2.2GHz |
Model 148 |
Model 248 |
Model 848 |
| 2.4GHz |
Model 150 |
Model 250 |
Model 850 |
| 2.6GHz |
Model 152* |
Model 252 |
Model 852 |
| Low-Power Options |
|
| EE (30W) Frequency |
Model Numbers |
| 1.4GHz |
Model 140 EE |
Model 240 EE |
Model 840 EE |
| HE (55W) Frequency |
Model Numbers |
| 2.0 GHz |
Model 146 HE |
Model 246 HE |
Model 846 HE |
| 2.2GHz |
Model 148 HE* |
Model 248 HE |
Model 848 HE* |
| Integrated memory controller |
Yes |
Yes |
Yes |
| Memory controller width |
128-bit |
128-bit |
128-bit |
| ECC DRAM protection |
Yes |
Yes |
Yes |
| HyperTransport™ Technology |
Yes |
Yes |
Yes |
| HyperTransport Links (total/coherent) |
Mar-00 |
1-Mar |
3-Mar |
| HyperTransport Link width |
16 bits x 16 bits |
16 bits x 16 bits |
16 bits x 16 bits |
| HyperTransport bus frequency |
800MHz |
800MHz |
800MHz |
| Or 1000MHz |
Or 1000MHz |
Or 1000MHz |
| AMD64 |
Yes |
Yes |
Yes |
| Simultaneous 32 & 64-bit computing |
Yes |
Yes |
Yes |
| |
64KB/64KB per core |
64KB/64KB per core |
64KB/64KB per core |
| L2 Cache Size |
1MB per core |
1MB per core |
1MB per core |
| Pipeline stages (integer/floating point) |
17-Dec |
17-Dec |
17-Dec |
| L1/L2 data cache protection |
ECC |
ECC |
ECC |
| L1/L2 instruction cache protection |
Parity |
Parity |
Parity |
| Global History Counter Entries |
16K |
16K |
16K |
| L1 TLB entries (data/instruction) |
40/40 |
40/40 |
40/40 |
| L1 associativity (data/instruction) |
Full/Full |
Full/Full |
Full/Full |
| L2 TLB entries (data/instruction) |
512/512 |
512/512 |
512/512 |
| L2 associativity (data/instruction) |
4-way/4-way |
4-way/4-way |
4-way/4-way |
| Direct Connect Architecture |
Yes |
Yes |
Yes |
| Process |
.13 or .09 micron SOI |
.13 or .09 micron SOI |
.13 or .09 micron SOI |
| Manufactured In |
Fab 30, Dresden |
Fab 30, Dresden |
Fab 30, Dresden |
| *Model planned for Q2'05 introduction. |
|
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